1. Field of the Invention
This invention relates to a method for mounting a semiconductor chip on a substrate and to a semiconductor device that is adapted for mounting on a substrate.
2. Description of the Related Art
With the rapid advancement in semiconductor fabrication technology, the bonding pads on the surface of a semiconductor chip are getting smaller in size, and the distance between adjacent bonding pads are getting shorter. These can create difficulty when connecting the semiconductor chip to an external circuit, and can affect adversely the production yield.
In the co-pending U.S. patent application Ser. No. 09/725,431, the applicant disclosed a method for mounting a semiconductor chip on a substrate to prepare a semiconductor device. The substrate has a chip-mounting region provided with a plurality of solder points. The semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region. The method involves the steps of: forming a plurality of conductive bumps, each of which is electrically connected to and is formed so as to protrude from a respective one of the bonding pads; forming a photoresist layer on the pad-mounting surface with a plurality of access holes, each of which is registered with and exposes at least a portion of one of the bumps; and forming a plurality of conductive bodies, each of which has an anchor portion filling one of the access holes and connected to and encapsulating the exposed portion of the respective one of the bumps, an extension portion extending from the anchor portion and formed on the surface of the photoresist layer, and a contact portion protruding from one end of the extension portion and formed on the surface of the photoresist layer opposite to the anchor portion. The contact portion is disposed at the position corresponding to a respective one of the solder points on the chip-mounting region of the substrate.
An object of the present invention is to provide a semiconductor device of the type disclosed in the aforesaid co-pending U.S. patent application Ser. No. 09/725,431 that is capable of overcoming the aforesaid drawback.
According to the present invention, a semiconductor device is adapted for mounting on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor device comprises: a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting surface; a plurality of conductive first bumps electrically and respectively connected to and protruding from the bonding pads; a photoresist layer formed on the pad-mounting surface of the semiconductor chip, the photoresist layer being formed with a plurality of access holes registered with and exposing at least a portion of a respective one of the first bumps on the bonding pads; and a plurality of conductive second bumps, each of which has a lower portion filling a respective one of the access holes to electrically connect with and encapsulate the portion of a respective one of the first bumps, and an upper portion extending from the lower portion and protruding from an upper surface of the photoresist layer opposite to the pad-mounting surface.
According to a further aspect of the present invention, a semiconductor device is adapted for mounting on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor device comprises: a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads; a photoresist layer formed on the pad-mounting surface of the semiconductor chip, the photoresist layer being formed with a plurality of access holes registered with and exposing at least a portion of a respective one of the bonding pads, each of the access holes being confined by a peripheral wall; a plurality of plating layers, each of which has a tubular lower portion that lines the peripheral wall of a respective one of the access holes and that is electrically connected to a respective one of the bonding pads, and an upper portion that lies on an upper surface of the photoresist layer around the respective one of the access holes; and a plurality of conductive bodies, each of which has an extension portion, and an anchor portion and a contact portion on opposite ends of the extension portion, the anchor portion filling an interior of the lower portion of a respective one of the plating layers, and encapsulating the upper portion of the respective one of the plating layers so as to connect electrically with the respective one of the bonding pads, the contact portion being formed on the upper surface of the photoresist layer and being disposed at the location corresponding to a respective one of the solder points on the chip-mounting region of the substrate, the extension portion being formed on the upper surface of the photoresist layer and interconnecting the anchor and contact portions.